IF Input Frequency: DC to 160 MHz selectable in 1Hz incr
Nominal Signal Level:
                  +3 to -25 dBm total power in IF bandwidth
Minimum Signal Level: -10 dBm total power in IF bandwidth
Maximum Signal Level: +10 dBm continuous, no damage
Acquisition Level: programmable sensitivity to 6 dB Eb/No
                          or -20 dB SNR
Loop Bandwidths (PSK): programmable from 0.5to 3%
                          of signal baud rate
Bit Sync Modes:
                          Single channel (e.g. BPSK)
                          Dual same-rate channels (e.g. QPSK, OQ)
                          Dual differing-rate channels (e.g. AQPSK, UQ)
Outputs: 3-bit Soft Decision and Clock for each channel

Output waveforms:

Either analog channel selectable to:

     baseband I/Q outputs compatible with external
          vector modulator
     modulated IF carrier from 50 Hz to 20 MHz in
          1 Hz increments
      phase representation of output waveform

Level from -10 to +4 dBm in 0.5 dBm increments
Independent I/Q Offset Control 0 to +/- .5 V in ~4 mV steps
Independent I/Q Level Control 0 to 1 V p-p in
     multiples of ~4 mV

Carrier Suppression (null carrier modulations): > 50 dB
Side lobe Suppression: >40 dB
PM Distortion: < 4°
FM Distortion; < 2%
Spurious Harmonics: > -30 dBc
Spurious Non-harmonics:
        > - 40 dBc< 100 KHZ
        > - 50 dBc< 200 KHZ
        > - 60 dBc< 3 MHZ
        > - 74 dBc> 3 MHZ

Phase Shift Keyed (PSK) - B, Q, OQ, AQ, UQ optional
                 phase shaping from 1-100% of baud period
                 in 12.5% increments
Phase Modulation (PM) - Digital or Analog
PM/PSK - Configurable subcarrier frequency
Frequency Modulation (FM) - Digital or Analog (i.e. FSK)
Demod bypass – bit-sync only
Consult factory for other or custom waveforms

Data Rates: 50 bps to 20 Mbps
Data Rate Selectivity: 0.001 Kbps steps
Acquisition/Tracking Range:

Programmable up to +/- 500 Hz in 1 Hz increments

Locking Threshold:

programmable sensitivity to 6 dB Eb/No or
                -23 dB SNR in IF bandwidth

Performance:

Typically within 0.5 dB of Theory for Typical Waveforms

RS-232 and/or Parallel Interface
Custom M&C interfaces available
Serial rates to 115.2 kbps
RS-232 Interface Functional Capabilities:

Load/verify all firmware elements
Invoke/monitor board level diagnostics
Set/verify all operational configurable parameters
Monitor all operational status information Invoke/monitor self-test

Parallel Interface Functional Capabilities:

Set/verify all operational configurable parameters
Monitor all operational status information
Invoke/monitor self-test

Supported Algorithms and Sequencing:
              Pre-decoder Phase/Merge/Symbol Ordering Control
        Viterbi Decoder
       PCM Decoder
       Data Descrambling
              Post-decoder Merge/Symbol Ordering Control
       Supported Modes:
              Dual (independent channel paths through decoder)
              Single (data merge (for Q phase demod modes prior                 to decode)
              Dual/merge (dual operation through Viterbi prior to
                data merge)
Phase /Symbol Ordering Modes:
              Single mode - I/Q, I/Q-, I-/Q, I-/Q-, Q/I, Q/I-, Q-/I, Q-/I-
       Dual modes – independent I or Q invert
       Automatic symbol order by micro-controller if
              Viterbi Decoder enabled
       Phase/Symbol ordering may be changed without
              causing demod reacquisition.
       Viterbi Configuration:
              Selectable on or off
              Constraint Length: 7 (K=7) rate 1/2
              Rate: 3/4 punctured code
              Polynomials G0=171 (octal), G1=133 (octal)
              Ordering G1/G2, G2/G1, G2/G1-, G2-/G1

PCM Decoder:
              Input formats : NRZ-L/M/S or BIØ-L/M/S
              Output format: NRZ-L
              BIØ modes based on soft decision
 Descrambling:
              Independently enabled/disabled for
                     parallel encoders
               Algorithms: V.35 (CCITT) or V.36 (INTELSAT)

Inputs and Modes:
       Two (2) independent data/clock I/O’s
       Clocks may be configured as input from user or
       output from UCP-4000
       Output clocks configurable from 50 bps to 20 Mbps
              in 1 Hz increments
       Input clock from 50 bps to 20 Mbps
       For single bit/baud modulations, either data/clock
              can be selected as input
       For synchronous 2 bit/baud modulations:
              Data or clock can drive single encoder prior to I/Q split
              Data or clock can be split even/odd to
                 fully parallel encoders
              Separate inputs can drive fully parallel encoders
       For UQPSK or AQPSK modulations,
              separate inputs can drive fully parallel encoders
              at same or different rates
Supported Algorithms and Sequencing:
              Data Scrambling
              PCM Encoder
       Convolutional Encoder
       Scrambling:
              Independently enabled/disabled for
                     parallel encoders
               Algorithms: V.35 (CCITT) or V.36 (INTELSAT)
PCM Encoder:
              Independently configured for parallel encoders
              Input format: NRZ-L
              Output formats : NRZ-L/M/S or BIØ-L/M/S
       Convolutional Encoder Configuration:
              Independently enabled/disabled for parallel encoders
              Constraint Length: 7 (K=7) rate ½
              Rate: 3/4 punctured code
              Polynomials G0=171 (octal), G1=133 (octal)
              Ordering G1/G2, G2/G1, G2/G1-, G2-/G1

Physical Characteristics:

Size/Connectors/Mounting per IEEE P1386
                   Common Mezzanine Card

Primary Power: +3.3 Vdc (+/- 5% @ 5 A max.
Temperature

0° TO 70° C Operational
-20° TO +85° C Storage